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      Instructor-Led (Classroom) Training

      Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.


      Jan
      18
      Jan
      21
      Bangalore, India
      2–6 PM IST
      English | 88776 INR

      Jan
      25
      Jan
      28
      Bangalore, India
      9–5 PM IST
      English | 88776 INR

      Mar
      3
      Mar
      5
      Hsinchu City, Taiwan
      9–5 PM CST
      Mandarin - Traditional | 900 USD

      Mar
      15
      Mar
      18
      Shanghai, China
      9–5 PM CST
      Mandarin - Simplified | 8652 CNY

      Apr
      20
      Apr
      22
      Hsinchu City, Taiwan
      9–5 PM CST
      Mandarin - Traditional | 900 USD

      Live Online Training

      Live Online classes deliver all the interactivity and depth of the traditional classroom, from the convenience of your own computer, with hands-on exercises and course materials.


      Mar
      1
      Mar
      10
      Live Online
      8–2 PM PM PST
      English | 2800 USD

      Mar
      16
      Mar
      19
      Live Online
      9–4 PM PM SGT
      English | 2000 USD

      May
      17
      May
      21
      Live Online
      8–2 PM PM IDT
      English | 6648 ILS

      Jun
      21
      Jun
      30
      Live Online
      9–3 PM PM CEST
      English | 2600 EUR

      Course Highlights

      Course Highlights

      You will learn how to

      • Write DRC rules that perform a full complement of layout dimensional checks
      • Write specification statements to control DRC output
      • Use Boolean and topological operators to derive new layer data
      • Debug rule files
      • Write polygon-directed and edge-directed checks
      • Write basic and enhanced antenna rule checks
      • Improve DRC run-time efficiency
      • Write equation-based DRC rule checks
      • Create and use layer properties
      • Write rules to establish layout connectivity
      • Write rules to recognize different devices such as MOS transistors, resistors and capacitors of different types, bipolar transistors etc. in the layout
      • Extend the set of built-in device templates to include your own custom devices
      • Extract various properties such as width, length, resistance and capacitance of recognized devices, using the Built-in property language within Calibre nmLVS TM and compare these values with those specified in the source netlist
      • Effectively utilize the text present in the GDSII layout database, and supplement it with text supplied through the rule file to annotate nets and ports • Optimally use the various Calibre statements that deal with net and port names in the layout
      • Write various LVS specification statements that control how the layout netlist extracted from the layout database is compared to the source netlist
      • Effectively block out selected cells during the LVS netlist comparison process
      • Call Calibre TVF routines from within device property computation functions
      • Access layout property data from within device property computation functions

      Hands-on labs

      • Preparing the Rule File and Running Calibre
      • Viewing DRC and LVS Results
      • Using the Online Documentation
      • Writing Layer Definitions
      • Writing DRC and LVS Specification Statements
      • Writing and Testing Dimensional Rule Checks
      • Designing and Testing Derived Layer Statements
      • Writing Polygon-directed Rule Checks
      • Designing and Testing Edge and Error-directed Rule Checks
      • Creating and Using Layer Properties
      • Writing and Testing Connectivity Statements
      • Designing and Testing Antenna Rule Checks
      • Taking Advantage of Hierarchy
      • Setting LVS Report Options
      • Finding Soft Connections
      • Creating and Naming Ports
      • Inserting Text Objects Into a Layout Using the Rule File
      • Writing Device Recognition Statements
      • Specifying Custom User-Defined Devices
      • Using the Built-In Language to Define Device Properties
      • Writing TVF code to generate a DRC rule file

      Prerequisites

      Completion of the Calibre nmDRC/nmLVS class is very highly recommended

      Thorough knowledge of IC layout techniques and procedures

      Experience with an IC layout editing tool Good understanding of SPICE netlists

      Familiarity with UNIX

      Good understanding of layout verification concepts and experience with layout verification tools

      Course Part Number

      Instructor-led: 058450
      Live online: 239707

      Guides

      Student workbook table of contents
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