Article Roundup: Siemens raises Capital to full E/E design level, Why Go Custom in AI Accelerators, Revisited, Post Layout Simulation Is Becoming The Bottleneck For Analog Verification, Real time operating systems: black box or open source?, How to gain a competitive edge with advanced DFT

1. Siemens raises Capital to full E/E design level
2. Why Go Custom in AI Accelerators, Revisited
3. Post Layout Simulation Is Becoming The Bottleneck For Analog Verification
4. Real time operating systems: black box or open source?
   
5. How to gain a competitive edge with advanced DFT

Siemens raises Capital to full E/E design level
TechDesignForum

Capital started out as a tool for harness design, but in its new incarnation stretches up to the architectural design and specification of E/E systems, as well as the capture and transfer of consistent data across multiple steps in the flow. In this article, the author discusses how these capabilities feed into a consistent “digital thread” that feeds into the concept of the digital twin at the heart of the Xcelerator platform.

Why Go Custom in AI Accelerators, Revisited
SemiWiki

This article throws light on the rapidly evolving range of possible AI architectures to justify differentiation in power, performance and cost through custom solutions. The highly-interactive Catapult workflow provides full visibility and control of the synthesis process, enabling designers to rapidly converge upon the best implementation for power, performance, and area. Furthermore, the author highlights how Catapult HLS helps build these custom accelerators and more.

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification
SemiEngineering

The Analog FastSPICE platform delivers the most accurate, most comprehensive, and highest-performance verification capabilities available in a single-executable platform and is foundry certified accurate by the world’s leading foundries at the most advanced process geometries, removing the analog verification bottleneck. In this article, the author highlights key components of high-performance, high-capacity and high-accuracy SPICE circuit simulation technology. The article also covers the challenges of nanometer circuit verification, closed loop PLL phase noise and how the verification is performed with the AFS platform.

Real time operating systems: black box or open source?
EDACafe

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To meet the power requirements of todays advanced designs, engineers can ease development with integrated power management in Nucleus that includes support for DVFS, deep sleep modes, and power/clock gating. In this article, Colin Walls dives deep into the advantages and disadvantages of real time operating systems (RTOS), multiple versions of OS, API calls and more.

How to gain a competitive edge with advanced DFT
ElectronicsWeekly

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This article highlights why, a winning DFT strategy is not just dependent on DFT tools, but also on the ecosystem around them. The author emphasizes on the need for a streamlined DFT flow, the importance of improved yield, and design for test strategies. Mentor’s Tessent DFT technologies, developed in partnership with industry leaders, provide the most advanced DFT and yield solutions available.

Today, AI processor designs are typically very large, consist of many duplicate processor arrays numbering in the hundreds or thousands and require high test coverage. There’s no way to manage this without a hierarchical DFT methodology that divides the task into smaller pieces. The coverage requirements include many fault models, which means embedded compression must also be aggressive.